For 20 ms a divider value shall be 31250Hz / 50Hz = 625, but 625 > 255 = PWM_MAX_PERIOD. So, a clock source 32kHz is not a way.
As I see an usage of REG_PWM_CLK (or Config PWM 29h) to select clock source is not implemented in SD Card Linux v1.0.3
It is required to rewrite cy8c9540a_pwm_config procedure and add REG_PWM_CLK register support.
