Cache Coherence Granularity

Hi all,

Empirically the cache line size of most processors is believed to be 64 Bytes. And it is indeed confirmed

in my Linux machine by checking out the file /proc/cpuinfo.

But my question is, what's the basic size of the cache coherence protocol inside the processor?

Supposing a MSI protocol, is it true that a single cache line is tagged as, say, "M" state, or, they

are tagged in a bigger granularity, such as 2 or 4 lines are packed together to be marked in the "M"

state?  Because according to my experience, it seems that the Xeon(R) CPU E5-2650 processor

tags two cache lines together.

Thank you very much.